Turning to FIG. 1, an example of a conventional system 100 can be seen. In this system 100, input data IN is provided to flip-flop 102. Flip-flop 102 can then generate an output signal for logic 104 in synchronization with an edge of clock signal CLK1 (which is generated from clock signal MCLK by clock tree 110). Logic 104 can then process the output from flip-flop 102, and the output of logic 104 can be provided to buffer 106. Here, buffer 106 is included to include a minimum path length to ensure that no output from logic 104 reaches flip-flop 108 prior to the generation of a corresponding phase or edge of clock signal CLK2 by tree 112 (which is also commonly referred to as a “hold violation”). As a result, the buffer 106 operates as a “hold buffer” that generally eliminates hold violations.
Use of hold buffers (like buffer 106) are very common and have worked very well in conventional applications, but there is an ever-increasing desire to reduce power consumption due at least in part to the increasing use of mobile products that employ batteries as a power sources. With this desire to decrease power consumption, operations of systems (such as system 100) in sub-threshold voltage ranges is becoming desirable. When operating in sub-threshold voltage ranges, though, hold buffers (i.e., buffer 106) can become problematic because the hold buffers (i.e., buffer 106) will increase the largest path length as well as the shortest path length, which can significantly degrade performance under some circumstances. Additionally, these hold buffers can further degrade performance when there are significant process and temperature variations coupled with use of supply voltages within sub-threshold ranges. Therefore, there is a need for a method and/or apparatus that compensates for hold violations within both super-threshold and sub-threshold supply voltage ranges.
Some examples of conventional systems are: U.S. Pat. No. 6,262,612; U.S. Pat. No. 7,978,004; U.S. Patent Pre-Grant Publ. No. 2001/0015665; U.S. Patent Pre-Grant Publ. No. 2003/0058017; U.S. Patent Pre-Grant Publ. No. 2008/0278223; and European Patent No. EP2320565.